1. Field of the Invention
The present invention relates to a method for fabricating a stencil mask and, more particularly, to a method for fabricating a stencil mask which can improve alignment accuracy of front and rear patterns.
2. Description of the Related Art
As the degree of integration of a semiconductor device increases, it is necessary to develop patterns having fine line widths. The smallest critical dimension that can be achieved with a particular system is a function of the light source used in the exposure process. Exceptionally fine patterns require the use of a light source having an extremely short wavelength.
For example, although G-line and I-line deep-UV light sources have been used recently in conventional exposure processes, a light source having a shorter wavelength such as electron beam, ion beam and X-ray is necessary to achieve even finer critical dimensions. Non-optical lithography processes using an electron beam, ion beam, or X-ray as the light source for exposing a photoresist layer provide superior resolution when compared to conventional optical lithography processes relying on G-line or I-line light sources. Thus, the non-optical lithography processes make it possible to form patterns having critical dimension smaller than those that can be obtained using one of the conventional optical lithography processes.
Although non-optical lithography processes had generally been used in manufacturing exposure masks, more recently these processes have been used in manufacturing non-memory devices such as logic devices and ASIC devices.
In non-optical lithography processes, a typical exposure mask, that is, an exposure mask having a Cr pattern provided on a quartz substrate, has not been used. Because electron beams, ion beams, and X-ray sources have short wavelengths of tenths of Angstroms to hundreds of Angstroms, they cannot be transmitted effectively through a typical exposure mask.
Accordingly, on/off type stencil masks have been used as exposure masks in non-optical lithography processes. The stencil mask is a general term for exposure masks used in non-optical lithography processes with electron beam, ion beam, or X-ray sources and includes cell projection masks.
The stencil mask consists of a frame acting as supporting means, a membrane formed over the frame for reducing the stress due to exposure to the light source and maintaining balance, and a pattern formed over the membrane for absorbing or scattering a portion of the projected light source directed onto the stencil mask.
In fabricating stencil masks, it has been conventional to use silicon on insulator (SOI) wafers. As is generally known, a SOI wafer has a structure wherein a buried oxide is sandwiched between a silicon substrate and a silicon film.
The prior art method of fabricating a stencil mask will now be described with reference to FIGS. 1A to 1F.
Referring to FIG. 1A, an SOI wafer 10 having a buried oxide film 2 and a silicon film 3 sequentially formed on a silicon substrate 1 is prepared.
Referring to FIG. 1B, a silicon oxide film 11 is then formed on the surface of the SOI wafer 10. A resist film is coated on the silicon oxide film 11 on the front surface of the SOI wafer 10, exposed, and developed to form a first resist pattern 12 that exposes a portion of the silicon oxide film 11.
Referring to FIG. 1C, the exposed portion of the silicon oxide film 11 is etched using the first resist pattern 12 as an etching mask to form a silicon oxide film pattern. The first resist pattern 12 is then removed and silicon film 3 is etched using the silicon oxide film pattern as an etching mask to form an absorber 3a and an alignment key 3b. The remaining portion of silicon dioxide film 11 is then removed from the wafer. The alignment key 3b is then used in patterning the rear, or backside, surface of the SOI wafer 10.
Referring to FIG. 1D, in order to prevent the absorber 3a from being damaged when patterning the rear surface of the SOI wafer, a silicon nitride film 13 is then deposited over the entire surface of the wafer. A resist film is coated on the silicon nitride film 13 on the rear surface of the SOI wafer, exposed, and developed to form a second resist pattern 14 that exposes a portion of the silicon nitride film on the rear surface of the SOI wafer. During the exposure of the resist film, the SOI wafer is aligned using the alignment key 3b. 
Referring to FIG. 1E, the silicon nitride film 13 formed on the rear surface of the SOI wafer is etched to a desired shape using the second resist pattern 14 as an etching mask. Silicon substrate 1 is then etched using the buried oxide 2 as an etching stop layer to form a frame 1a. 
Referring to FIG. 1F, the second resist pattern 14 and the silicon nitride film are removed. After that, the exposed part of the buried oxide 2 is then typically removed with a wet etch process to complete the on/off type stencil mask 20.
However, this prior art method for fabricating stencil masks is deficient in several respects.
The rear surface patterning process applied to the rear surface of the SOI wafer 10, that is, the formation of the second resist pattern 14, is performed using the alignment key 3b formed on the front surface of the SOI wafer 10. The frame is then formed by etching the silicon layer 1 using the second resist pattern 14. However, it is impossible to check the alignment state after forming the second resist pattern. As a result, in instances in which the second resist pattern is misaligned relative to the first pattern, the frame produced after completion of the etching process is similarly misaligned. Particularly, where the frame misalignment blocks any portion of the aperture intended for transmitting through the stencil mask, the resulting stencil mask is defective.
The alignment state of the second resist pattern can be checked by another alignment apparatus at the rear surface of the structure shown in FIG. 1D. However, due to the cost of the apparatus and the valuable processing time required to check the alignment state of the second resist pattern in this manner, it is difficult to justify using the alignment apparatus regularly in a manufacturing environment.
Therefore, it is an object of the present invention to provide a method for fabricating a stencil mask that will provide improved alignment accuracy between the front and the rear patterns.
To accomplish this object, there is provided a method for fabricating a stencil mask comprising the steps of: preparing a SOI wafer having a transparent insulating film and a silicon film sequentially formed on a silicon substrate; forming an absorber pattern, including an alignment key, on the insulating film by patterning the silicon film, forming a first silicon nitride film on the resultant entire surface; forming a first resist pattern that exposes desired portions of a first silicon nitride film under the alignment key on a first silicon nitride film of the rear surface of the silicon substrate; forming an alignment window on the part of the silicon substrate under the alignment key by etching the first silicon nitride film and the silicon substrate using the first resist pattern as an etching mask; removing the first resist pattern, forming a second silicon nitride film on the inner wall of the alignment window; forming a second resist pattern restricting a frame forming area on the first and the second silicon nitride films under the silicon substrate by checking the alignment state of the alignment key through the alignment window; forming a frame by etching the first silicon nitride film and silicon substrate using a second resist pattern as an etching mask; removing the second resist pattern and the first and the second silicon nitride films; and removing the exposed part of the insulating film.